ds4106/ds4212/ds4425 106.25mhz/212.5mhz/425mhz clock oscillators rev 2; 4/08 general description the ds4106, ds4212, and ds4425 ceramic surface-mount crystal oscillators are part of maxim? ds4-xo series of crystal oscillators. these devices offer output frequencies at 106.25mhz, 212.5mhz, and 425mhz. the clock oscillators are suited for systems with tight tol- erances because of the jitter, phase noise, and stability performance. the small package provides a format made for applications where pcb space is critical. these clock oscillators are crystal based and use a fun- damental crystal with pll technology to provide the final output frequencies. each device is offered with lvds or lvpecl output types. the output enable pin is active-high logic. these clock oscillators have very low phase jitter and phase noise. typical phase jitter is < 0.9ps rms from 12khz to 20mhz. the devices are designed to operate with a 3.3v ?0% supply voltage, and are available in a 5.0mm x 3.2mm x 1.49mm, 10-pin lccc surface-mount ceramic package. applications fibre channel hard disk driveshost bus adapters raid controllers fibre channel switches features ? clock output frequencies: ds4106: 106.25mhzds4212: 212.50mhz ds4425: 425.00mhz ? phase jitter (rms): 0.9ps typical ? lvpecl or lvds output ? supply current: 50ma (typical, unloaded) at +3.3v supply (lvpecl) 53ma (typical) at +3.3v supply (lvds) ? -40? to +85? temperature range ? output disable v cc - 2v 100 50 lvpecl option lvds option 50 v cc v cc v cc gnd oe outp outn 100 v cc v cc v cc gnd oe outp outn lvpecl lvds ds4106/ds4212/ ds4425 ds4106/ds4212/ ds4425 typical operating circuits pin configuration and selector guide appear at end of data sheet. ________________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. + denotes a lead(pb)-free package. the lead finish is jesd97 category e4 (au over ni) and is compatible with both lead-based and lead-free soldering processes. ordering information part temp range pin-package ds4106 an+ -40 c to +85 c 10 lccc ds4106bn+ -40 c to +85 c 10 lccc ds4212 an+ -40 c to +85 c 10 lccc DS4212BN+ -40 c to +85 c 10 lccc ds4425 an+ -40 c to +85 c 10 lccc ds4425bn+ -40 c to +85 c 10 lccc downloaded from: http:///
ds4106/ds4212/ds4425 106.25mhz/212.5mhz/425mhz clock oscillators 2 _______________________________________________________________________________________ electrical characteristics(v cc = 3.0v to 3.6v, t a = -40? to +85?, typical values are at v cc = +3.3v and t a = +25?, unless otherwise noted.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc , gnd, oe, outp, outn .....................................-0.3v, +4v operating temperature range ...........................-40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-40 c to +125 c soldering temperature profile (3 passes max) ...............................see ipc/jedec j-std-020 specification parameter symbol conditions min typ max units supply voltage v cc (note 2) 3.0 3.3 3.6 v lvpecl (note 3) 50 65 supply current i cc lvds 53 67 ma ttl control input-voltage high (oe) v ih (note 2) 2 v cc v ttl control input-voltage low (oe) v il (note 2) 0 0.8 v input leakage current i il gnd oe v cc -50 +10 a lvpecl outputs (note 4) output high voltage v oh (note 2) v cc - 1.085 v cc - 0.88 v output low voltage v ol (note 2) v cc - 1.825 v cc - 1.62 v output leakage current (absolute) i ol oe = v il 100 a lvds outputs (figure 2) lvds output high voltage v oh (note 2) 1.475 v lvds output low voltage v ol (note 2) 0.925 v lvds differential output voltage | v od | 250 400 lvds change in v od for complementary states | v od | 25 mv lvds offset output voltage (output common-mode voltage) v os (note 5) 1.125 1.275 v absolute maximum ratings downloaded from: http:///
ds4106/ds4212/ds4425 106.25mhz/212.5mhz/425mhz clock oscillators _______________________________________________________________________________________ 3 electrical characteristics (continued)(v cc = 3.0v to 3.6v, t a = -40? to +85?, typical values are at v cc = +3.3v and t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units lvds change in v os for complementary states | v os | 150 mv lvds differential output impedance r olvdso 80 140 lvds output current i lvdso outputs shorted together 12 ma output current i vsslvdso short to ground 40 ma clock output ds4106 106.25 ds4212 212.5 clock output frequency f o ds4425 425.0 mhz frequency stability total f / f o temperature, aging, load, and supply -39 +39 ppm initial frequency tolerance f _tol +25 c, 3 c, v cc = 3.3v 20 ppm frequency stability vs. temperature f / f o | ta -30 +30 ppm frequency stability vs. v cc f / f o | v v cc = 3.3v 10% -3 +3 ppm/v frequency stability vs. load f / f o | load 10% variation in termination resistance 1 ppm aging (15 years) f aging -7 +7 ppm phase jitter (rms) pj rms 12khz to 20mhz 0.9 ps 10khz 3 100khz 27 200khz 15 accumulated deterministic jitter due to power-supply noise (p-p) 1mhz 7 ps lvpecl 200 clock output edge speeds t r , t f 20% to 80% lvds 175 ps clock output duty cycle +25c 45 55 % oscillation startup time (note 6) 10 ms downloaded from: http:///
ds4106/ds4212/ds4425 106.25mhz/212.5mhz/425mhz clock oscillators 4 _______________________________________________________________________________________ note 1: limits at -40? are guaranteed by design and are not production tested. note 2: voltage referenced to ground. note 3: outputs are enabled and unloaded. note 4: when the lvpecl output is disabled, the typical output off current is < 100? for nominal lvpecl signal levels at the output. note 5: ac parameters are guaranteed by design and characterization. note 6: including oscillator startup time and pll acquisition time, measured after v cc reaches 3.0v from power-on. electrical characteristics (continued)(v cc = 3.0v to 3.6v, t a = -40? to +85?, typical values are at v cc = +3.3v and t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units 100hz -90 1khz -112 10khz -115 100khz -123 1mhz -142 ds4106 at 106.25mhz 10mhz -147 100hz -82 1khz -106 10khz -109 100khz -117 1mhz -136 ds4212 at 212.50mhz 10mhz -141 100hz -76 1khz -100 10khz -103 100khz -111 1mhz -130 clock output ssb phase noise ds4425 at 425.00mhz 10mhz -135 dbc/hz downloaded from: http:///
ds4106/ds4212/ds4425 pin description pin name function 1 oe output enable. on-chip pullup resistor. connect oe to logic-high, v cc , or leave open to enable the output clock. connect oe to logic-low or gnd to disable the output clock. the lvpecl output clock is set to high impedance when disabled. the lvds output clock is latched to a differential high when disabled. 2, 7C10 n.c. no connection 3 gnd ground 4 outp positive clock output, lvpecl or lvds 5 outn negative clock output, lvpecl or lvds 6 v cc +3.3v supply ep exposed paddle. do not connect this pad or place exposed m etal under the pad. oscillator amplifier pfd counter n loop filter vco counter m output buffer v cc v cc outpoutn oe gnd ds4106/ds4212/ ds4425 detailed description the ds4106/ds4212/ds4425 combine a crystal and anic to form a precision clock. figure 1 shows a function- al diagram of the devices. the ic consists of a crystal oscillator, a low-noise pll, selectable clock-divider cir- cuitry, and an output buffer. the pll consists of a digi- tal phase/frequency detector (pfd) and low-jitter generation vco. the vco signal is scaled by a clock- divider circuit and applied to the output buffer. output drivers all devices are available with either lvpecl(ds4106a/ds4212a/ds4425a) or lvds (ds4106b/ ds4212b/ds4425b) output buffers. when not needed, the output buffers can be disabled. when disabled, the lvpecl output buffer goes to a high-impedance state. however, the lvds outputs go to a differential logic one (outp latched high and outn latched low) when the outputs are disabled. additional information for more available frequencies, refer to the ds4125data sheet at www.maxim-ic.com/ds4125 . figure 1. functional diagram 106.25mhz/212.5mhz/425mhz clock oscillators _______________________________________________________________________________________ 5 downloaded from: http:///
ds4106/ds4212/ds4425 106.25mhz/212.5mhz/425mhz clock oscillators 6 _______________________________________________________________________________________ + denotes a lead-free package. the lead finish is jesd97 category e4 (au over ni) and is compatible with both lead-based and lead- free soldering processes. d rl = 100 dc ivodi single-ended output outp differential output outn 0v (diff) v oh v os v ol -v od +v od vodp - p = voutp - voutn figure 2. lvds level definitions selector guide part outputs frequency (mhz) top mark ds4106 an+ lvpecl 106.25 06a ds4106bn+ lvds 106.25 06b ds4212 an+ lvpecl 212.50 12a DS4212BN+ lvds 212.50 12b ds4425 an+ lvpecl 425.00 42a ds4425bn+ lvds 425.00 42b downloaded from: http:///
ds4106/ds4212/ds4425 106.25mhz/212.5mhz/425mhz clock oscillators _______________________________________________________________________________________ 7 thermal information 12 3 65 4 top view oe n.c. n.c. *ep *exposed pad n.c. n.c. n.c. gnd v cc outnoutp + (5.00mm 3.20mm 1.49mm) ds4106/ds4212/ ds4425 pin configuration theta-ja (c/w) 90 package type package code document no. 10 lccc l1053+h2 21-0389 package information for the latest package outline information and land patterns, goto www.maxim-ic.com/packages . downloaded from: http:///
ds4106/ds4212/ds4425 106.25mhz/212.5mhz/425mhz clock oscillators maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2008 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 7/07 initial release. in the general descripion section, corrected power-supply tolerance from 5% to 10%. 1 1 10/07 in the electrical characteristics table, added the input voltage max value of v cc and input voltage min of 0 for v ih and v il ; added gnd oe v cc for conditions on input leakage (i il ); corrected accumulated deterministic jitter due to reference spurs parameter to accumulated deterministic jitter due to pow er- supply noise. 2, 3 in the electrical characteristics table, changed the clock output frequency (f o ) typ from 106.2mhz to 106.25mhz. 3 2 4/08 in the pin description, changed the exposed pad description to indicate that it should not be connected and to avoid placing exposed metal under the pad location. 5 downloaded from: http:///
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